1. Field of the Invention
The present invention relates to a memory control apparatus and method.
2. Description of the Related Art
As the semiconductor and microprocessor technologies progress, the field of application of embedded systems is steadily expanding. Most popular electronic and electric devices use embedded systems. Additionally, along with the recent increase in integration of LSIs, a so-called system LSI is becoming common which integrates the controller function of an embedded device in one LSI.
FIG. 7 is a view showing a configuration that implements an embedded system of OA equipments by using a system LSI disclosed in, e.g., U.S. Pat. No. 6,480,916.
Referring to FIG. 7, a system LSI 100, memory 101, and various kinds of IO interfaces are mounted on an embedded system board 110. The system LSI 100 is a single-chip scanning printing engine. More specifically, the system LSI 100 incorporates a processor core, processor peripheral controller, memory controller, scanner controller, printer controller, PCI interface, and USB device interface.
The IO interfaces provided on the embedded system board 110 are a scanner IF 131, FAX IF 132, USB IF 134, and printer IF 133. These IO interfaces are connected to a scanner 121, FAX 122, PC 124, and printer engine 123 to form the entire system. The system LSI 100 also has a PCI bus IF 136. With the PCI bus IF 136, an HDD 125 connected to an IDE bus 135 can be used through a PCI-IDE bridge 102.
FIG. 2 is a block diagram for explaining the system LSI 100 in more detail.
A processor 201 can incorporate a cache memory of 32 Kbytes (16 Kbytes for each of instruction and data), FPU (Floating Point Unit), MMU (Memory Management Unit), and user-definable coprocessor.
Since a PCI bus interface 232 is present, the system LSI 100 can be used together with a computer system having a PCI bus slot. In addition to the PCI satellite configuration, the PCI host bus bridge configuration can issue a PCI bus configuration. Hence, when combined with an inexpensive PCI peripheral device, the system LSI 100 can be used as the main engine of a multifunction peripheral. The system LSI 100 can also be combined with a rendering engine or compression/decompression engine having a PCI bus interface.
The chip incorporates two independent buses, i.e., an IO bus (B bus) 221 to connect a general-purpose IO core and a graphics bus (G bus) 220 optimized for image data transfer. A memory 204 (101), the processor 201, and these buses are connected through a system bus bridge 203 serving as a cross bus switch. With this configuration, high-speed parallel data transfer necessary for simultaneous operation in a multifunction system is implemented.
The system LSI 100 also incorporates a memory controller 202 that supports a synchronous DRAM (SDRAM) with high cost performance for access to a continuous data sequence represented by image data.
The system LSI 100 also incorporates a scanner controller 205, printer controller 206, PCI controller 207, USB controller 208, UART 209, MISC module 210 including a timer/GPIO function, and LAN controller 211. Reference numerals 230 to 233 denote IO interfaces of the controllers 205 to 208. These IO interfaces are identical to the interfaces 131, 133, 134, and 136 with the same names in FIG. 7.
FIG. 3 is a timing chart for explaining the sequence of a typical composite operation. In this example, a so-called copy operation is executed in which the scanner 121 scans a document, and the printer engine 123 prints the scanned document. Image data obtained by scanning a document is transmitted from the scanner 121 to the scanner controller 205 incorporated in the system LSI 100 through the scanner interface 131 (230) (301). The scanner controller 205 stores the received image data in the memory 204 (101) by DMA (302). The printer controller 206 reads out the data from the memory 204 by DMA (303) and transmits the data to the printer engine 123 through the printer interface 231 (133) (304). The printer engine 123 prints the data.
At this time, PDL data is also transmitted from the PC 124 through the USB interface 134 (233) (311). The PDL data is received by the USB device controller 208 and temporarily stored in the memory 204 by DMA (312). The PDL data is interpreted by the processor 201 in the system LSI 100. The bitmapped image is stored in the memory 204 again (313). Finally, the image data is read out from the memory 204 by the printer controller 206 (314), transmitted to the printer engine 123 through the printer interface 231 (133) (315), and printed.
FIG. 4 shows a physical address space handled by the processor 201 at this time. Actually, the processor 201 is compatible with MIPS R4000. Software on the processor 201 runs by using a virtual address. The processor 201 always operates in a kernel mode. Physical addresses 0x0000—0000 to 0x1fff_ffff correspond to virtual addresses 0x8000—0000 to 0x9fff_ffff (kseg0: cached) and 0xa000—0000 to 0xbfff_ffff (kseg1: uncached).
In this prior art, the memory 204 has a capacity of 32 MB and incorporates a 256-Mbit SDRAM with a 16-bit×4-bank×4M-word configuration. Hence, the physical address space usable as a RAM corresponds to addresses 0x0000—0000 to 0x0 ff_ffff.
When the composite operation shown in FIG. 3 is executed, software running on the processor 201 manages the buffer area on the memory 204 used by hardware. Like a normal case wherein a memory area is dynamically ensured by software, an area with a necessary size is ensured in the Heap area by using a memory allocate function (a system function provided by the OS: e.g., malloc).
In the composite operation shown in FIG. 3, the buffer area write-accessed by the scanner controller 205 by DMA is the same as the buffer area read-accessed by the printer controller 206 by DMA. If there is only one buffer area, the address written by the scanner controller 205 is read out by the printer controller 206 later. However, the speed of read from a scanner and the speed of printing by a printer are normally different. Hence, if there is no mechanism for synchronizing the scanner controller 205 with the printer controller 206, the read address may go ahead of the write address.
To avoid this, the buffer is generally doubled. More specifically, while the scanner controller 205 write-accesses one buffer area by DMA, the printer controller 206 read-accesses the other buffer area by DMA. When DMA transfer of both controllers is ended, the buffers to be used by them are replaced, and next DMA is started.
For example, when 1-MB data is continuously transmitted from the scanner 121 to the scanner controller 205, the argument of the memory allocate function is set to 1 MB and called. The returned address is (converted from a virtual address to a physical address) set to the DMA start address of the scanner controller 205. In this case, addresses 0x0080—0000 to 0x008f_ffff are ensured, and the first address 0x0080—0000 is set to the DMA start address. When data arrives, the scanner controller 205 continuously stores the data from the start address by DMA. When DMA is ended, the address 0x0080—0000 is set to the DMA start address of the printer controller 206. When software instructs to start DMA, the data is sequentially read out from the set start address in accordance with the signal of the printer interface 231 and transferred to the printer engine 123 through the printer interface 231.
At the same time, the next DMA setting is done for the scanner controller 205. The argument of the memory allocate function is set to 1 MB and called again. When addresses 0x0090—0000 to 0x009f_ffff are ensured, the first address 0x0090—0000 is set to the DMA start address. When data from the scanner interface 230 arrives, the scanner controller 205 continuously stores the data from the start address by DMA.
In this way, the DMA operation is repeatedly executed while using the two areas corresponding to the addresses 0x0080—0000 to 0x008f_ffff and 0x0090—0000 to 0x009f_ffff in alternate order between the scanner controller 205 and the printer controller 206.
For the USB controller 208, addresses 0x00b0—0000 to 0x00bf_ffff are ensured, and the first address 0x00b0—0000 is set to the DMA start address. When data is transmitted from the PC (USB host) 124, the USB controller 208 continuously stores the data from the start address by DMA. When all transfer is ended, the software is notified of it by an interrupt. Next, the software interprets PDL data and generates print image data. The finally generated print image data is stored in a newly ensured buffer area. To do this, the memory allocate function is called again to ensure a 3-MB area corresponding to addresses 0x00c0—0000 to 0x00ef_ffff. The address 0x00c0—0000 is set to the DMA start address, and the printer controller 206 is activated. DMA transfer of the printer controller 206 at this time is executed exclusively of DMA transfer of the printer controller 206 in the above-described scanner printer operation.
As described above, when the scanner and printer simultaneously access the HDD, a plurality of hardware devices simultaneously DMA-access the memory in the system LSI.
When a plurality of masters issue access requests for only one memory source in the system LSI, the access requests always conflict at a certain probability. For, e.g., the printer controller that must continuously supply data to the printer engine, an increase in latency in case of access confliction must be taken into consideration. Hence, the FIFO capacity to buffer the data rate must be large to deal with the worst delay value. This increases the circuit scale and chip cost. In addition, various adverse effects such as an increase in heat and a decrease in reliability occur.
For example, assume that 32-byte data is transferred in one cycle of DMA transfer. If the capacity of the FIFO memory is only 32 bytes, the next DMA transfer cycle can start after the FIFO becomes vacant. This configuration cannot be used when data must continuously be supplied to the printer engine once the printer operation starts, like the above-described printer controller. The FIFO is always required to have a capacity to store data of a plurality of DMA transfer cycles. The FIFO needs to have a capacity for at least two DMA transfer cycles, i.e., a capacity of 64 bytes.
Assume the printer interface has a FIFO with a capacity of 64 bytes. When the contents of the FIFO decrease to 32 bytes or less, the printer interface can issue the next DMA transfer request to the memory controller. When the next data is read out from the memory and written in the FIFO by DMA transfer before the FIFO becomes vacant, data can continuously be supplied to the printer engine.
If there is no master issuing a memory access request simultaneously as the printer interface issues a DMA transfer request to the memory controller, the data can be read out and stored in the FIFO before the FIFO becomes vacant. However, if another master has issued an access request to the memory controller immediately before, the printer controller cannot read out the data from the memory and store it in the FIFO until the memory access request is processed.
Under some circumstances, data read by the printer controller may delay along with the increase in delay time, and the FIFO may be vacant meanwhile.
To avoid this, the printer controller has a FIFO capacity of at least, e.g., 128 bytes to prevent any problem even in the worst case. If memory conflict rarely occurs, a capacity of 64 bytes or 96 bytes at best suffices in most cases. However, to deal with a rare case, the circuit scale is increasing.